This invention relates to a high speed arithmetic processing circuit, particularly to a high speed arithmetic processor with internal adders or subtracters which is capable of high speed arithmetic processing and which can be implemented using LSI technology.
An example of a conventional high speed divider is found in Takagi et al., "A VLSI Oriented High Speed Divider Using Redundant Binary Representation," Trans. Inst. of Electronics and Comm. Engi. Japan, Vol. J67-D, No. 4, pp. 450-457, where a divider is based on a shift subtract divide method wherein each digit is represented by a digit set [-1, 0, 1] which is the redundant binary representation and which is realized by using combinational circuitry which includes four input NOR/OR gates implemented by Emitter-Coupled-Logic (ECL).
This prior art divider is superior to other types of conventional dividers in terms of operating speed and regularity of element layout. However, little consideration was given to reducing the number of transistor elements and the reducing the area on a semiconductor chip required to realize the divider, and to the possibility of using different types of circuit elements, such as CMOS.
Conventional dividers realized by sequential circuitry which consists of a subtracter (or adder) and a shifter are also well known. However, it is also well known that this type of divider inevitably requires relatively long computation time as the number of digits increases. While a high capacity computer with a high speed multiplier which employs a multiplicative division method is known, such prior art devices also require large amounts of hardware to realize the combinational circuitry, making this approach impractical.